The present technique relates to an apparatus and method for accessing an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of virtual addresses to physical addresses. The provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks to memory required in order to obtain the required address translation data.
Nevertheless, as systems require ever higher performance, the timing requirements for performing a lookup within the address translation cache in order to determine whether the required address translation data is present can limit the address translation cache's capacity, and thereby have a performance impact. In addition, the high rate of access and use of large gates to meet the frequency target can lead to significant power consumption. For example, to seek to ensure a high hit rate, a level one TLB may be implemented as a fully associative structure, but the lookup process then requires a check in respect of each of the entries of the level one TLB in order to determine if a hit is present. The lookup process involves using the virtual address to check against corresponding virtual address bits in each of the TLB entries, and this approach has timing and power implications.
Accordingly, it would be desirable to provide an improved mechanism for accessing an address translation cache.